Logic analyzers have traditionally had two basic modes of data acquisition: synchronous and asynchronous. Synchronous data acquisition, or state analysis as it is also known, refers to the process of acquiring data at times determined by the active edge of the user's system clock signal. Asynchronous data acquisition, or timing analysis, refers to the process of acquiring data at times determined by the active edge of a clock that is generated by the logic analyzer. Asynchronous data acquisition is typically performed at sampling rates that are faster than the user's system clock in order to provide a closer look at the timing of particular signals.
A third kind of data, known as "glitch" data has also been acquired by logic analyzers. A "glitch" is usually defined as more than one transition across the logic threshold within one data acquisition interval, i.e., within the interval between successive active edges of the acquisition clock. For example, three transitions and a change in logic state, or two transitions and the same logic state, are both defined as glitches. More thorough discussions of glitches and means for detecting them are contained in U.S. Pat. Nos. 4,353,032, 4,843,255, and 4,857,760 for a "Glitch Detector", a "Self-Latching Monostable Circuit", and a "Bipolar Glitch Detector Circuit", respectively, all hereby incorporated by reference.
When glitches are being acquired, keeping track of glitch data requires as much memory as the corresponding data acquisition does. This is because every active clock edge on which data is sampled has associated with it the interval between that edge and the next edge during which a glitch can occur. Therefore, when glitches are being acquired, half of the available memory must be dedicated to storing glitch data. This means that either half of the memory depth or half of the memory width is utilized for this function.
To conserve the amount of memory required for data storage, "transitional" data storage is now frequently employed, especially in conjunction with asynchronous data acquisition. In this approach, rather than storing the logic state of a signal upon the occurrence of every acquisition clock signal, no data is stored for acquisition clock cycles in which no data has changed. When the data does change, the new data is stored along with a timestamp that provides a record of the time when the new data was acquired. Thus, memory is only used in direct proportion to the number of logic state transitions and, even though extra memory is required to store the timestamps, a considerable amount of memory is conserved in most circumstances.
It is frequently desirable to acquire both synchronous and asynchronous data in relationship to the same event. For example, if a hardware problem is suspected in certain circuitry, but it only seems to occur during specific kinds of operations, it might be desirable to use synchronous acquisition to monitor microprocessor operations until the specific kind of operation is occurring, and then trigger asynchronous data acquisition in the vicinity of the certain circuitry to learn more about the suspected problem.
In the past, this sort of cross-triggering of asynchronous acquisition by events detected through synchronous acquisition was accomplished by two logic analyzers, or two distinct portions of a single logic analyzer. However, this requires double probing of the circuitry under analysis. Also, when using two separate logic analyzers, the user must perform a calculation to determine the timing relationship between the synchronous data and the asynchronous data. When using a logic analyzer with integrated synchronous and asynchronous sections, the delay from probe tip to trigger machine and between trigger machines for each section may not be accurately aligned to place the timing data in the desired relationship with a synchronous event of interest.
Even in advanced logic analyzers, such as those in the Philips PM 3580 Family, which eliminate dual probing and provide a single trigger machine for both state and timing analysis, memory is pre-allocated to state, timing, or equally to both in advance. This is an inefficient use of memory when the user's interest in the data does not conform to these pre-allocations.